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CY22392
Three-PLL General Purpose FLASH Programmable Clock Generator
Features

Improves frequency accuracy over temperature, age, process, and initial offset. Non-Volatile programming enables easy customization, ultra-fast turnaround, performance tweaking, design timing margin testing, inventory control, lower part count, and more secure product supply. In addition, any part in the family can also be programmed multiple times which reduces programming errors and provides an easy upgrade path for existing designs. In-house programming of samples and prototype quantities is available using the CY3672 FTG Development Kit. Production quantities are available through Cypress Semiconductor's value added Distribution partners or by using third party programmers from BP Microsystems, HiLo Systems, and others. Performance suitable for high-end multimedia, communications, industrial, A/D Converters, and consumer applications. Supports numerous low-power application schemes and reduces EMI by allowing unused outputs to be turned off. Adjust Crystal Drive Strength for compatibility with virtually all crystals. 3-Bit External Frequency Select Options for PLL1, CLKA, and CLKB. Industry-standard supply voltage. Industry-standard packaging saves on board space. Easy to use software support for design entry.
Three integrated phase-locked loops Ultra Wide Divide Counters (8-bit Q, 11-bit P, and 7-bit Post Divide) Improved Linear Crystal Load capacitors Flash programmability Field programmable Low-jitter, high-accuracy outputs Power-management options (Shutdown, OE, Suspend) Configurable Crystal drive strength Frequency Select through 3 external LVTTL Inputs 3.3V operation 16-pin TSSOP packages CyClocksRTTM Support

Benefits
Generates up to 3 unique frequencies on 6 outputs up to 200 MHz from an external source. Functional upgrade for current CY2292 family. Allows for 0 ppm Frequency Generation and Frequency Conversion under the most demanding applications.
Logic Block Diagram
XTALIN XTALOUT OSC. XBUF
CONFIGURATION FLASH
PLL1 11 BIT P 8 BIT Q PLL2 11 BIT P 8 BIT Q PLL3 11 BIT P 8 BIT Q 4x4 Crosspoint Switch
Divider /2,3, or 4
CLKE
SHUTDOWN/OE S0 S1 S2/SUSPEND
Divider 7 BIT Divider 7 BIT
CLKD
CLKC
Divider 7 BIT Divider 7 BIT
CLKB
CLKA
Cypress Semiconductor Corporation Document #: 38-07013 Rev. *E
*
198 Champion Court
*
San Jose, CA 95134-1709 * 408-943-2600 Revised October 10, 2008
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CY22392
Pinouts
Figure 1. CY22392 - 16-pin TSSOP
CLKC VDD AGND XTALIN XTALOUT XBUF CLKD CLKE 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 SHUTDOWN/OE S2/SUSPEND AVDD S1 S0 GND CLKA CLKB
Pin Definitions
Name CLKC VDD AGND XTALIN XTALOUT XBUF CLKD CLKE CLKB CLKA GND S0 S1 AVDD S2/ SUSPEND SHUTDOWN/OE Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Description Configurable clock output C Power supply Analog Ground Reference crystal input or external reference clock input Reference crystal feedback Buffered reference clock output Configurable clock output D Configurable clock output E Configurable clock output B Configurable clock output A Ground General Purpose Input for Frequency Control; bit 0 General Purpose Input for Frequency Control; bit 1 Analog Power Supply General Purpose Input for Frequency Control; bit 2. Optionally Suspend mode control input. Places outputs in three-state condition and shuts down chip when LOW. Optionally, only places outputs in tristate condition and does not shut down chip when LOW
Document #: 38-07013 Rev. *E
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CY22392
Operation
The CY22392 is an upgrade to the existing CY2292. The new device has a wider frequency range, greater flexibility, improved performance, and incorporates many features that reduce PLL sensitivity to external system issues. The device has three PLLs which, when combined with the reference, allow up to four independent frequencies to be output on up to six pins. These three PLLs are completely programmable.
applications that requirements.
are
sensitive
to
absolute
frequency
The value of the load capacitors is determined by six bits in a programmable register. The load capacitance can be set with a resolution of 0.375 pF for a total crystal load range of 6 pF to 30 pF. For driven clock inputs the input load capacitors may be completely bypassed. This enables the clock chip to accept driven frequency inputs up to 166 MHz. If the application requires a driven input, then XTALOUT must be left floating.
Configurable PLLs
PLL1 generates a frequency that is equal to the reference divided by an 8-bit divider (Q) and multiplied by an 11-bit divider in the PLL feedback loop (P). The output of PLL1 is sent to the crosspoint switch. The output of PLL1 is also sent to a /2, /3, or /4 synchronous post-divider that is output through CLKE. The frequency of PLL1 can be changed by external CMOS inputs, S0, S1, S2. See the following section on General-Purpose Inputs for more details. PLL2 generates a frequency that is equal to the reference divided by an 8-bit divider (Q) and multiplied by an 11-bit divider in the PLL feedback loop (P). The output of PLL2 is sent to the crosspoint switch. PLL3 generates a frequency that is equal to the reference divided by an 8-bit divider (Q) and multiplied by an 11-bit divider in the PLL feedback loop (P). The output of PLL3 is sent to the cross-point switch.
Output Configuration
Under normal operation there are four internal frequency sources that may be routed through a programmable crosspoint switch to any of the four programmable 7-bit output dividers. The four sources are: reference, PLL1, PLL2, and PLL3. In addition, many outputs have a unique capability for even greater flexibility. The following is a description of each output. CLKA's output originates from the crosspoint switch and goes through a programmable 7-bit post divider. The 7-bit post divider derives its value from one of two programmable registers. Each of the eight possible combinations of S0, S1, S2 controls which of the two programmable registers is loaded into CLKA's 7-bit post divider. See the section "General-Purpose Inputs" for more information. CLKB's output originates from the crosspoint switch and goes through a programmable 7-bit post divider. The 7-bit post divider derives its value from one of two programmable registers. Each of the eight possible combinations of S0, S1, and S2 controls which of the two programmable registers is loaded into CLKA's 7-bit post divider. See the section "General-Purpose" Inputs for more information. CLKC's output originates from the crosspoint switch and goes through a programmable 7-bit post divider. The 7-bit post divider derives its value from one programmable register. CLKD's output originates from the crosspoint switch and goes through a programmable 7-bit post divider. The 7-bit post divider derives its value from one programmable register. CLKE's output originates from PLL1 and goes through a post divider that may be programmed to /2, /3, or /4. XBUF is simply the buffered reference. The Clock outputs have been designed to drive a single point load with a total lumped load capacitance of 15 pF. While driving multiple loads is possible with the proper termination it is generally not recommended.
General-Purpose Inputs
S0, S1, and S2 are general-purpose inputs that can be programmed to allow for eight different frequency settings. Options that may be switched with these general purpose inputs are as follows; the frequency of PLL1, the output divider of CLKB, and the output divider of CLKA. CLKA and CLKB both have 7-bit dividers that point to one of two programmable settings (register 0 and register 1). Both clocks share a single register control, so both must be set to register 0, or both must be set to register 1. For example: the part may be programmed to use S0, S1, and S2 (0,0,0 to 1,1,1) to control eight different values of P and Q on PLL1. For each PLL1 P and Q setting, one of the two CLKA and CLKB divider registers can be chosen. Any divider change as a result of switching S0, S1, or S2 is guaranteed to be glitch free.
Crystal Input
The input crystal oscillator is an important feature of this device because of its flexibility and performance features. The oscillator inverter has programmable drive strength. This allows for maximum compatibility with crystals from various manufacturers, processes, performances, and qualities. The input load capacitors are placed on-die to reduce external component cost. These capacitors are true parallel-plate capacitors for ultra-linear performance. These were chosen to reduce the frequency shift that occurs when non-linear load capacitance interacts with load, bias, supply, and temperature changes. Non-linear (FET gate) crystal load capacitors must not be used for MPEG, POTS dial tone, communications, or other
Power Saving Features
The SHUTDOWN/OE input three-states the outputs when pulled LOW. If system shutdown is enabled, a LOW on this pin also shuts off the PLLs, counters, the reference oscillator, and all other active components. The resulting current on the VDD pins is less than 5 A (typical). After leaving shutdown mode, the PLLs will have to relock. The S2/SUSPEND input can be configured to shut down a customizable set of outputs and/or PLLs, when LOW. All PLLs and any of the outputs can be shut off in nearly any combination. The only limitation is that if a PLL is shut off, all outputs derived from it must also be shut off. Suspending a PLL shuts off all Page 3 of 9
Document #: 38-07013 Rev. *E
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CY22392
associated logic, while suspending an output simply forces a three-state condition.
can download a copy of CyClocksRT for free on Cypress's web site at www.cypress.com.
Improving Jitter
Jitter Optimization Control is useful in mitigating problems related to similar clocks switching at the same moment, causing excess jitter. If one PLL is driving more than one output, the negative phase of the PLL can be selected for one of the outputs (CLKA-CLKD). This prevents the output edges from aligning, allowing superior jitter performance.
Junction Temperature Limitations
It is possible to program the CY22392 such that the maximum Junction Temperature rating is exceeded. The package JA is 115 C/W. Use the CyClocksRT power estimation feature to verify that the programmed configuration meets the Junction Temperature and Package Power Dissipation maximum ratings.
Power Supply Sequencing
For parts with multiple VDD pins, there are no power supply sequencing requirements. The part is not be fully operational until all VDD pins have been brought up to the voltages specified in the "Operating Conditions" table. All grounds must be connected to the same ground plane.
Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested. Supply Voltage................................................-0.5V to +7.0V
DC Input Voltage ........................... -0.5V to + (AVDD + 0.5V) Storage Temperature ................................. -65C to +125C Junction Temperature .................................................. 125C Data Retention at Tj = 125C .................................>10 years Maximum Programming Cycles........................................100 Package Power Dissipation...................................... 350 mW Static Discharge Voltage (per MIL-STD-883, Method 3015) .......................................... 2000V Latch up (per JEDEC 17) .................................... > 200 mA
CyClocksRTTM Software
CyClocksRT is our second-generation application that allows users to configure this device. The easy-to-use interface offers complete control of the many features of this family including input frequency, PLL and output frequencies, and different functional options. Data sheet frequency range limitations are checked and performance tuning is automatically applied. CyClocksRT also has a power estimation feature that allows you to see the power consumption of your specific configuration. You
Operating Conditions[1]
Parameter VDD/AVDD TA CLOAD_OUT fREF Supply Voltage Commercial Operating Temperature, Ambient Industrial Operating Temperature, Ambient Max. Load Capacitance External Reference Crystal External Reference Clock[2], Commercial External Reference Clock tPU
[2],
Description
Min 3.135 0 -40 - 8 1 1 0.05
Typ. 3.3 - - - - - - -
Max 3.465 +70 +85 15 30 166 150 500
Unit V C C pF MHz MHz MHz ms
Industrial
Power up time for all VDD's to reach minimum specified voltage (power ramps must be monotonic)
Notes 1. Unless otherwise noted, Electrical and Switching Characteristics are guaranteed across these operating conditions. 2. External input reference clock must have a duty cycle between 40% and 60%, measured at VDD/2.
Document #: 38-07013 Rev. *E
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CY22392
Switching Characteristics
Parameter 1/t1 t2 Name Output Frequency
[3, 4]
Description Clock output limit, Commercial Clock output limit, Industrial Duty cycle for outputs, defined as t2 / t1, Fout < 100 MHz, divider >= 2, measured at VDD/2 Duty cycle for outputs, defined as t2 / t1, Fout > 100 MHz or divider = 1, measured at VDD/2
Min. - - 45% 40% 0.75 0.75 - - -
Typ. - - 50% 50% 1.4 1.4 150 400 1.0
Max. 200 166 55% 60% - - 300 - 3
Unit MHz MHz
Output Duty Cycle[3, 5]
t3 t4 t5 t6 t7
Rising Edge Slew Rate[3] Output clock rise time, 20% to 80% of VDD Falling Edge Slew Rate[3] Output three-state Timing[3] Clock Jitter[3, 6] Lock Time[3] Output clock fall time, 20% to 80% of VDD Time for output to enter or leave three-state mode after SHUTDOWN/OE switches Peak-to-peak period jitter, CLK outputs measured at VDD/2 PLL Lock Time from Power up
V/ns V/ns ns ps ms
Switching Waveforms
Figure 2. All Outputs, Duty Cycle and Rise/Fall Time
t1 t2 OUTPUT t3 t4
Figure 3. Output Three-State Timing
OE t5 ALL THREE-STATE OUTPUTS t5
Figure 4. CLK Output Jitter
t6 CLK OUTPUT
Notes 3. Guaranteed by design, not 100% tested. 4. Guaranteed to meet 20%-80% output thresholds and duty cycle specifications. 5. Reference Output duty cycle depends on XTALIN duty cycle. 6. Jitter varies significantly with configuration. Reference Output jitter depends on XTALIN jitter and edge rate.
Document #: 38-07013 Rev. *E
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CY22392
Switching Waveforms (continued)
Figure 5. Frequency Change
SELECT
OLD SELECT Fold
NEW SELECT STABLE t7 Fnew
OUTPUT
Test Circuit
AVDD 0.1 F OUTPUTS CLK out CLOAD VDD 0.1 F GND
Document #: 38-07013 Rev. *E
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CY22392
Ordering Information
Ordering Code CY22392FC
[8]
Package Name Z16 Z16
Package Type 16-TSSOP 16-TSSOP - Tape and Reel 16-TSSOP 16-TSSOP - Tape and Reel 16-TSSOP 16-TSSOP - Tape and Reel FTG Programmer CY22392F, CY22393F CY22394F and CY22395F Adapter for CY3672-USB
Operating Range Commercial (TA = 0C to 70C) Commercial (TA = 0C to 70C) Commercial (TA = 0C to 70C) Commercial (TA = 0C to 70C) Industrial (TA = -40C to 85C) Industrial (TA = -40C to 85C)
Operating Voltage 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V
CY22392FCT[8] CY22392ZC-XXX CY22392ZI-xxx CY3672-USB CY3698
[7, 8]
Z16 Z16 Z16 Z16
CY22392ZC-XXXT[7, 8]
[7, 8] [7, 8]
CY22392ZI-xxxT
Pb Free CY22392FXC CY22392FXCT CY22392FXI CY22392FXIT CY22392ZXC-xxx[7] CY22392ZXC-xxxT[7] CY22392ZXI-xxx[7] CY22392ZXI-xxxT[7] Z16 Z16 Z16 Z16 Z16 Z16 Z16 Z16 16-TSSOP 16-TSSOP - Tape and Reel 16-TSSOP 16-TSSOP - Tape and Reel 16-TSSOP 16-TSSOP - Tape and Reel 16-TSSOP 16-TSSOP - Tape and Reel Commercial (TA = 0C to 70C) Commercial (TA = 0C to 70C) Industrial (TA = -40C to 85C) Industrial (TA = -40C to 85C) Commercial (TA = 0C to 70C) Commercial (TA = 0C to 70C) Industrial (TA = -40C to 85C) Industrial (TA = -40C to 85C) 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V
Note 7. The CY22392ZC-XXX, CY22392ZI-xxx, CY22392ZXC-xxx, and CY22392ZXI-xxx are factory programmed configurations. Factory programming is available for high-volume design opportunities of 100 Ku/year or more in production. For more details, contact your local Cypress FAE or Cypress Sales Representative. 8. Not recommended for new designs.
Document #: 38-07013 Rev. *E
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CY22392
Package Diagram
Figure 6. 16-lead TSSOP 4.40 MM Body Z16.173
PIN 1 ID
1
DIMENSIONS IN MM[INCHES] MIN. MAX. REFERENCE JEDEC MO-153
6.25[0.246] 6.50[0.256] 4.30[0.169] 4.50[0.177]
PACKAGE WEIGHT 0.05 gms PART # Z16.173 STANDARD PKG. ZZ16.173 LEAD FREE PKG.
16
0.65[0.025] BSC.
0.19[0.007] 0.30[0.012]
1.10[0.043] MAX.
0.25[0.010] BSC GAUGE PLANE 0-8
0.076[0.003] 0.85[0.033] 0.95[0.037] 0.05[0.002] 0.15[0.006] SEATING PLANE 0.50[0.020] 0.70[0.027] 0.09[[0.003] 0.20[0.008]
4.90[0.193] 5.10[0.200]
51-85091-*A
Document #: 38-07013 Rev. *E
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CY22392
Document History Page
Document Title: CY22392 Three PLL General Purpose Flash Programmable Clock Generator Document Number: 38-07013 REV. ** *A ECN 106738 108515 Orig. of Change TLG JWK Submission Date 07/03/01 08/23/01 Description of Change New Data Sheet Updates based on characterization results. Removed "Preliminary" heading. Added paragraph on Junction Temperature limitations and part configurations. Removed soldering temperature rating. Split crystal load into two typical specs representing digital settings range. Changed t5 max to 300 ns. Changed t7 typical to 1.0 ms. Preliminary to Final. Power up requirements added to Operating Conditions Information Added Lead Free Devices Updated template. Added Note "Not recommended for new designs." Added part number CY22392FC, CY22392FCT, CY22392ZC-XXXT, CY22392ZI-xxxT, CY3672-USB, CY3698, CY22392FXCT, CY22392FXIT, CY22392ZXC-xxxT, and CY22392ZXI-xxxT, in ordering information table. Removed part number CY22392FI in ordering information table. Changed Lead-Free to Pb-Free.
*B *C *D *E
110052 121864 237811 2584052
CKN RBI RGL AESA
12/09/01 12/14/02 See ECN 10/10/08
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer's representatives, and distributors. To find the office closest to you, visit us at cypress.com/sales.
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(c) Cypress Semiconductor Corporation, 2001-2008. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress' product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement.
Document #: 38-07013 Rev. *E
Revised October 10, 2008
Page 9 of 9
CyClocksRT is a trademark of Cypress Semiconductor Corporation. All products and company names mentioned in this document may be the trademarks of their respective holders.
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